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Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)

ISBN: 0852964439
EAN: 2147483647

Year: 2004
Pages: 100

Authors: Yichuang Sun

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• Table of Contents
• BackCover
• Wireless Communication Circuits and Systems
• Preface
• Chapter 1: Wireless Communications and Transceivers - an Overview
• 1.2 Integrated circuit technologies for wireless systems
• 1.3 Transceivers for wireless and mobile communications
• 1.4 Challenging topics in communication circuits and systems
• 1.5 Summary of chapters
• Chapter 2: Non-Complex Signal Processing in a Low-IF Receiver
• 2.2 Evolution of integrated receiver architectures
• 2.3 Digitising a conventional low-IF architecture
• 2.4 Performance requirements
• 2.5 Receiver dimensions
• 2.6 The change to non-complex signal processing
• 2.7 System simulations
• 2.8 Incorporation in a dual-mode receiver
• 2.9 Conclusions
• 2.10 References
• Chapter 3: A Reconfigurable Baseband Chain for 3G Wireless Receivers
• 3.2 Low-noise fully differential voltage buffer
• 3.3 Reconfigurable baseband chain for 3G receivers
• 3.4 Conclusions
• 3.5 References
• Chapter 4: Field-Programmable and Reconfigurable Analogue and Mixed-Signal Arrays
• 4.2 Field-programmable analogue arrays (FPAA)
• 4.3 Commercial FPAA products
• 4.4 Continuous-time CMOS OTA-C FPAA for high frequencies
• 4.5 FPMA and SoPC
• 4.6 Reconfigurable universal transceivers using FPAAs
• 4.7 Conclusions
• 4.8 References
• Chapter 5: A Low-Power, Low-Voltage Bluetooth Channel Filter Using Class AB CMOS Transconductors
• 5.2 Filter synthesis
• 5.3 Class AB CMOS transconductor
• 5.4 Filter design
• 5.5 Performance
• 5.6 Conclusions
• 5.7 References
• Chapter 6: Design and Automatic Tuning of Integrated Continuous-Time Filters
• 6.2 Filters in transceivers and the need for tuning
• 6.3 Filter architectures and design methods
• 6.4 On-chip tuning of continuous-time filters
• 6.5 Conclusions
• 6.6 References
• Chapter 7: Low-Voltage Integrated RF CMOS Modules and Frontend for 5 GHz and Beyond
• 7.2 A versatile low-voltage CMOS LNA topology
• 7.3 A CMOS VCO architecture suitable for sub-1 volt GHz-range applications
• 7.4 A very low-voltage (0.8 V) 5 GHz CMOS receiver frontend
• 7.5 Conclusions
• 7.6 References
• Chapter 8: Design of Integrated CMOS Power Amplifiers for Wireless Transceivers
• 8.2 Power amplifiers (PAs): concepts and challenges
• 8.3 Power amplifier controllability and stability
• 8.4 Recent progress in RF CMOS PA design
• 8.5 Conclusions
• 8.6 References
• Chapter 9: Parasitic-Aware RF IC Design and Optimisation
• 9.2 On-chip inductor modelling
• 9.3 Parasitic-aware optimisation
• 9.4 RF circuit syntheses
• 9.5 Conclusions
• 9.6 References
• Acknowledgements
• Chapter 10: Testing of RF, Analogue and Mixed-Signal Circuits for Communications - an Embedded Approach
• 10.2 Some analogue performance metrics and test fundamentals
• 10.3 Translating design specifications into production test programmes
• 10.4 The (diminishing) role of test equipment
• 10.5 Embedded mixed-signal test cores
• 10.6 Circuit considerations and instrument performance evaluation
• 10.7 Measurement types and test examples
• 10.8 Conclusions
• 10.9 References
• Index
• Index_B
• Index_C
• Index_D
• Index_E
• Index_F
• Index_G
• Index_H
• Index_I
• Index_J
• Index_K
• Index_L
• Index_M
• Index_N
• Index_O
• Index_P
• Index_Q
• Index_R
• Index_S
• Index_T
• Index_U
• Index_V
• Index_W-Y
• Index_Z
• List of Figures
• List of Tables