3.3 Reconfigurable baseband chain for 3G receivers

3.3 Reconfigurable baseband chain for 3G receivers

As shown in the previous sections, the DDA is a versatile element that can be used as a building block for designing filter and VGA sections. Design of a specific baseband chain can be achieved by cascading these sections. The number of sections used depends mainly on the wireless standard at hand as well as the ADC resolution. This specifies the required filter attenuation and the VGA control range. For multistandard operation, it is desirable to have a baseband chain where the number of filter and VGA sections used can be varied for each standard. The order in which the gain and filtering blocks are arranged directly affects the performance of the receiver in terms of linearity (IIP3), noise and dynamic range. Therefore a baseband chain with filter and VGA blocks that can be reconfigured in different arrangements is highly desirable. Such a chain will result in more optimized reception and will provide a programmable solution that can be easily re-configured to various demands.

To meet these requirements, the structure shown in Figure 3.15 is proposed. The baseband section consists of VGA and filter blocks that can be digitally programmed by the DSP at two levels. At the individual block level, the DSP sets the gain of the VGA sections as well as the cut-off frequency of the filters to accommodate different wireless standards. At the architecture level, the DSP controls interconnection of the blocks. This is done by using analogue switch arrays that enable each block to be connected to the analogue bus.

Figure 3.15: Block diagram of the reconfigurable receiver

For different wireless standards, the filter/VGA combination can be configured in various orders. Extra filter and VGA sections are turned off to reduce total power consumption. In each configuration the baseband chain provides a different gain control range, out-of-band signal attenuation, input referred noise and IIP3. To illustrate this, the chain is programmed in several different configurations as shown in Figure 3.16. Various parameters for each configuration are reported in Table 3.2. Here OIP3 is the output referred IP3 and SFDR is the spurious free dynamic range. In configuration (a) of Figure 3.16, the three filter sections are placed at the beginning of the chain. Two filters are used in their non-tuneable form. This is done by short-circuiting the gate of the triode region MOS transistor to analogue ground. The third filter section is tuneable and is used to reject nearby channels. The VGA sections are all cascaded after the filter sections.

Table 3.2: Results summary for different receiver configurations

Configuration	Noise (nV)	OIP3 (dBm)	SFDR	Power (mW)	Att. @ 1.6 MHz	Gain
(a)	22.6	29	73.4	7.7	97	48
(b)	31.88	26.7	69.8	6.5	95	48
(c)	20	26	72.5	7.7	96	48
(d)	45.6	35.3	68.2	7.7	150	54
(e)	35.1	31.5	68.3	6.5	95	48
(f)	105.2	30.7	64.1	5.4	97	48
(g)	109.5	34.2	64.6	6.5	151	54

Figure 3.16: Block diagram showing the different ways in which the proposed receiver architecture can be configured

In this configuration, excellent attenuation of out-of-band blockers is achieved, and the intermodulation products are strongly reduced. Furthermore, linearity of the VGA sections used is not crucial. However, cascading three filter sections without amplification decreases the signal-to-noise ratio and hence the input referred noise is expected to increase. Thus, in this configuration noise is traded off to achieve a receiver chain with high linearity and low intermodulation distortion. The chain is then programmed to be configured differently. In configuration (c) a VGA section is used at the beginning of the chain to improve overall noise performance. The VGA section is followed by a filter section to prevent further amplification of the out-of-band blockers. This filter section is subjected to large out-of-band blocker signals, and hence is configured in the non-tuneable mode to enhance linearity. For further attenuation of the blockers a tuneable filter section is cascaded next. Finally, amplification is done by placing two VGA sections at the end of the chain. Various signal levels through the chain in this configuration are shown in Figure 3.17. The chain is configured to receive a GSM signal with a bandwidth of 100 kHz. Attenuation of the blocker signals at 1.6 MHz and 3 MHz is also shown in the figure. Clearly, the programmable and reconfigurable features of the proposed receiver chain will allow the designer to quickly and easily trade-off between different design parameters without the need of redesigning the entire receiver chain. This approach helps in reducing the design time for the analogue portion of the wireless receivers. Furthermore, in terms of performance, the programmable nature of the chain allows a different configuration to be used for each standard, hence more optimum reception is possible.

Figure 3.17: Signal level through the receiver chain